TSMC Unveils 1.4nm Process and Technology Roadmap at North America Technology Forum

On April 23, TSMC hosted its 2025 North America Technology Forum, showcasing major advancements in semiconductor technology and outlining a comprehensive roadmap for the future. The event emphasized breakthroughs in artificial intelligence (AI), high-performance computing (HPC), and advanced packaging technologies.

TSMC Introduces A14 Process Technology, 1.4nm Node Targeted for 2028

The highlight of TSMC's announcement was the debut of the A14 process, a 1.4nm-class advanced node aimed at delivering faster performance and improved energy efficiency. A14 technology is designed to drive the next wave of AI transformation and enhance on-device intelligence for smartphones.

TSMC revealed that A14 will surpass the capabilities of its current 3nm nodes and the upcoming 2nm generation. Utilizing the second-generation GAAFET (Gate-All-Around Field Effect Transistor) architecture and optimized NanoFlex Pro technology, A14 will deliver a 15% speed boost or up to 30% power reduction compared to N2 technology, alongside a 20% increase in logic density. Mass production is planned for 2028, with derivative versions such as A14P, A14X, and A14C tailored for performance, optimization, and cost-sensitive applications.

3nm Family Expands: N3P in Mass Production, N3X Coming Soon

TSMC confirmed that N3P technology, the third generation of its 3nm process, has entered mass production as scheduled in Q4 2024. N3P delivers a 5% performance boost or a 5-10% reduction in power consumption compared to N3E, while maintaining full IP compatibility.

Following N3P, N3X is slated for mass production later this year. N3X promises an additional 5% performance improvement or a 7% power reduction. N3X also supports operating voltages up to 1.2V, pushing the performance boundaries for HPC applications, although it requires careful management of leakage currents.

Next-Generation Packaging: SoW-X Set for 2027 Launch

TSMC also unveiled System-on-Wafer-X (SoW-X), a revolutionary wafer-scale packaging technology. SoW-X can integrate at least 16 large computing chips, memory modules, and optical interconnects onto a dinner-plate-sized substrate, supporting power levels up to several kilowatts.

Targeted for HPC and AI workloads, SoW-X will deliver up to 40 times the computing capability of current CoWoS solutions. TSMC plans to commence volume production of SoW-X in 2027. Additionally, TSMC aims to expand CoWoS capabilities to accommodate up to 12 or more stacked HBM units by 2027.

TSMC Showcases New N4C RF and N3A Technologies

In addition to its flagship announcements, TSMC highlighted several new technologies across mobile, automotive, and IoT sectors:

N4C RF: Designed for mobile AI edge devices, N4C RF technology achieves 30% reductions in power and area compared to N6RF+, supporting Wi-Fi 8 and advanced AI-driven wireless applications. Pilot production is expected in early 2026.

N3A for Automotive: TSMC is finalizing qualification for its automotive-grade N3A node, targeting the growing software-defined vehicle market. N3A production will meet stringent automotive defect standards (DPPM).

N6e and N4e for IoT: As N6e enters mass production, TSMC is developing N4e, an ultra-low power node aimed at maximizing energy efficiency for future edge AI applications.

With its aggressive push into 1.4nm, advanced 3nm derivatives, revolutionary packaging, and industry-specific solutions, TSMC continues to solidify its leadership position in the semiconductor industry.