NEO Semiconductor Unveils Next-Gen 3D X-DRAM Aiming to Boost DRAM Density by 10x

May 9, 2025 — U.S.-based memory innovator NEO Semiconductor has announced a major leap in dynamic random-access memory (DRAM) architecture with the launch of its new-generation 3D X-DRAM technology, featuring the industry’s first 1T1C and 3T0C 3D DRAM cell designs. This breakthrough is set to redefine memory performance and scalability for high-demand applications in AI, edge computing, and in-memory processing.

The company revealed its latest innovation on May 7, emphasizing a vision to deliver unmatched memory density, power efficiency, and scalability. Built on a 3D NAND-like architecture, the new designs combine DRAM performance with NAND manufacturability, paving the way for high-yield, cost-effective production of memory chips with densities up to 512Gb — a tenfold increase over conventional DRAM.

Key Technologies: 1T1C and 3T0C 3D X-DRAM

1T1C Cell Design: Combines one transistor and one capacitor using a 3D NAND-like stack. Leveraging IGZO (Indium Gallium Zinc Oxide) channels, this design enhances data retention and is well-suited for AI and in-memory computing environments.

3T0C Cell Design: Utilizes three IGZO-based transistors — a write transistor, read transistor, and storage transistor — eliminating the capacitor and enabling electron-based data retention directly in the gate. This structure supports current-sensing readout, which is ideal for next-generation computing tasks.

Technical Highlights

Extended Retention Time: Thanks to IGZO channels, both 1T1C and 3T0C cells demonstrate data retention exceeding 450 seconds, dramatically reducing refresh power consumption.

Fast Read/Write Speeds: TCAD (Technology Computer-Aided Design) simulations show read/write latency of just 10 nanoseconds, rivaling modern DRAM performance levels.

Manufacturing Compatibility: Built on modified 3D NAND processes, the technology is designed for easy integration into existing DRAM fabs with minimal changes.

High Bandwidth Efficiency: A unique hybrid bonding array structure boosts bandwidth while lowering power draw, addressing growing demands from AI and HPC workloads.

Application-Ready: Tailored for AI training, edge computing, and data-intensive memory applications, 3D X-DRAM is positioned to meet the needs of advanced system architectures.

NEO Semiconductor’s CEO Andy Hsu described the technology as a major step in overcoming the scaling limitations of traditional DRAM. The 1T1C and 3T0C 3D X-DRAM architectures are part of the company’s ongoing roadmap to disrupt the status quo of memory technology.

In recent years, NEO Semiconductor has been recognized for its innovations in the 3D NAND and DRAM sectors. In 2023, the company introduced the world’s first 3D NAND-like DRAM architecture, and in August 2024, it launched its 3D X-AI chip technology, aiming to replace HBM in AI GPU accelerators.