TSMC to Begin Small-Scale Production of Panel-Level Packaging by 2027

Taiwan Semiconductor Manufacturing Company (TSMC) is preparing to enter the next frontier in advanced packaging technology, with its panel-level packaging (PLP) process nearing completion. According to Nikkei Asia, TSMC plans to begin small-scale production of PLP technology by 2027, setting a new milestone for the global semiconductor industry.

Unlike conventional wafer-level packaging that uses 300mm round wafers, TSMC’s PLP will utilize 310mm x 310mm square panels. The company has already established a pilot production line in Taoyuan, Taiwan, aiming to test and refine the process ahead of initial deployment. This shift to panel substrates not only represents a technological leap but could also redefine the standards across the entire semiconductor supply chain, prompting adjustments from equipment manufacturers to materials suppliers.

TSMC’s PLP and Global Expansion Strategy

TSMC’s PLP development also includes its fan-out panel-level packaging (FOPLP) technology, designed to offer superior thermal performance over traditional 3D stacking methods. Although current production efficiency still lags behind advanced 3D packaging techniques, FOPLP is expected to gain momentum as demand for high-performance AI chips accelerates.

In parallel, TSMC is ramping up construction of its Arizona-based fabrication facilities in the United States. The second fab is being readied ahead of schedule, with plans to start 3nm chip production by the end of 2027, followed by 2nm mass production in 2028. These efforts reflect TSMC’s proactive strategy to align capacity with major clients like AMD and NVIDIA, and respond to geopolitical pressures and supply chain diversification.

TSMC’s push into panel-level packaging could revolutionize chip design and integration by enabling higher throughput, better thermal characteristics, and reduced production costs over time. If successful, it will mark a pivotal moment not only for TSMC but for the broader adoption of panel-based semiconductor packaging technologies.