Processor Cores - Quad-core ARM Cortex [email protected]- 32KB I-Cache, 32KB D-Cache /512KB L3 cache - Neon acceleration support, integrated FPU processing unit - Built-in 32bit MCU@500MHz - 32KB I-Cache, 32KB D-Cache /64KB TCM - TrustZone support |
Intelligent Video Analytics - Image analytics acceleration engine with up to 10.4Tops@INT8 power
- Dual-core heterogeneous engine
- Engine 1 supports 4.8Tops, supports INT4/INT8/FP16
- Engine 2 supports 5.6Tops @ INT8/INT16.
- Supports complete API and toolchain for easy customer development.
- Support TrustZone
- Supports USB3.0 and PCIe2.0 high-speed interfaces.
- Dual-core Vision Q6 DSP
- 32K I-Cache /32K D-Cache /32K IRAM/320K DRAM
- Built-in Intelligent Computing Acceleration Engine
- Built-in binocular depth acceleration unit
- Built-in Matrix Computing Acceleration Unit |
Video Codec - H.264 BP/MP/HP
- H.265 Main Profile
- H.264/H.265 codec with maximum resolution 8192 x 8192
- H.264/H.265 encoding supports I/P frames.
- H.264/H.265 multi-stream encoding capability:
- 3840 x 2160@60fps + 1280x720@30fps
- 7680 x 4320@15fps
- H.264/H.265/MPEG-4 multi-stream decoding capability:
- 3840 x 2160@60fps + 1920x1080@60fps
- Supports pre-encoding OSD overlay of up to 8 regions
- Support CBR/VBR/AVBR/FIXQP/QPMAP and other bit rate control modes.
- Maximum output bit rate 160Mbps
- Supports 8 regions of interest (ROI) encoding.
- Support JPEG Baseline codec
- JPEG codec maximum resolution 16384x16384
- JPEG Maximum Performance
- Encoding: 3840 x 2160@60fps (YUV420)
- Decoding: 3840 x 2160@75fps (YUV420) |
Video Input Interface - Support 8-Lane image sensor serial input, support MIPI/LVDS/Sub-LVDS/HiSPi interfaces.
- Support 2x4-Lane or 4x2-Lane and other combinations, support up to 4-way sensor serial inputs.
- Maximum resolution 8192 x 8192
- Support 8/10/12/14 Bit RGB Bayer DC timing video input, clock frequency up to 150MHz.
- Support BT.601, BT.656, BT.1120 video input interface
- Support mainstream CMOS level thermal imaging sensor |
Digital Image Processing ISP - ISP supports time division multiplexing for processing multiple sensor input videos.
- Supports 3A (AE/AWB/AF) function, 3A control is user adjustable.
- Supports Fixed Pattern Noise (FPN)
- Supports bad dot correction and lens shadow correction;
- Supports up to three frames of WDR and Advanced Local Tone Mapping.
- Supports multi-level 3D noise removal, image edge enhancement, defogging, dynamic contrast enhancement and other processing functions.
- Support 3D-LUT color adjustment
- Supports lens distortion correction and fisheye correction.
- Supports 6-DoF digital stabilization and Rolling-Shutter correction.
- Supports image Mirror, Flip, 90 degree/270 degree rotation.
- Provides PC ISP adjustment tool
- Supports Hyper Sensitive Noise Reduction (HNR). |
Video and Graphics Processing Support 1/15.5～16x zoom function for graphics and images.
- Support up to 4-way video panorama splicing
- Input 2 3840x2160, output 4320x3840
- Input 4-way 2688x1520, output 6080x2688
- Support video layer and graphics layer overlay
- Support color space conversion |
Video Output - Support HDMI2.0 interface output
- Support 4-Lane Mipi DSI/CSI interface output, up to 2.5Gbps/lane.
- Built-in analog SD CVBS output
- Support 8/16/24 bit RGB, BT.656, BT.1120 and other digital interfaces.
- Support 2 independent HD video outputs at the same time
- Support any two interfaces non-simultaneous output
- One of them can support PIP (Picture In Picture)
- Maximum output capacity 4096x2160@60fps + 1920x1080@60fps |
Audio interface and processing - Built-in Audio codec, support 16bit voice input and output
- Support I2S interface
- Support multichannel time-division multiplexing transmission mode (TDM)
- Supports HDMI Audio output
- Realize multi-protocol voice codec through software
- Supports audio 3A (AEC/ANR/ALC) processing.
- Support audio 3A (AEC/ANR/ALC) processing Support G.711/G.726/AAC/etc. audio coding format |
Secure Isolation and Engine - Support for Secure Boot
- Supports TrustZone-based REE/TEE hardware isolation scheme
- Hardware implementation of AES symmetric encryption algorithm
- Hardware implementation of RSA2048/3072/4096 signature verification algorithm
- Hardware implementation of HASH-based SHA/256/384/512 and HMAC_SHA256/384/512 algorithms.
- Hardware implementation of random number generator
- Integration of 30Kbit OTP storage space for customer use. |
Network Interfaces - 2 Gigabit Ethernet interfaces
- Support RGMII, RMII two interface modes
- Supports acceleration units such as TSO, UFO, COE, etc.
- Support Jumbo Frame |
Peripheral Interface - Supports power-on reset (POR) and external input reset
- Integrated 4-channel LSADC
- Multiple UART, I²C, SPI, GPIO interfaces
- 2 SDIO3.0 interfaces
- SDIO0 support SDXC card, the maximum capacity of 2TB
- SDIO1 support wifi module docking
- 2 USB3.0/USB2.0 interfaces
- USB0 Host only
- USB1 Host/Device switchable
- 2-Lane PCIe2.0 High Speed Interface
- Supports RC/EP mode
- Configurable as 2-Lane PCIe2.0
- Configurable as 1-Lane PCIe2.0 + USB3.0 |
External Memory Interface - DDR4/LPDDR4/LPDDR4x Interface
- Supports 4 x 16bit DDR4
- Support 2 x 32bit LPDDR4/LPDDR4x
- DDR4 up to 3200Mbps
- LPDDR4/LPDDR4x up to 3733Mbps
- Maximum capacity 8GB
- SPI Nor/SPI Nand Flash Interface
- Supports 1, 2, and 4-wire modes
- SPI Nor Flash supports 3Byte, 4Byte address mode.
- NAND Flash Interface
- Support SLC, MLC asynchronous interface devices
- Support 2/4/8/16KB page size
- Support 8/16/24/28/40/64bit ECC (in 1KB unit)
- eMMC5.1 interface, maximum capacity 2TB
- Optional boot from eMMC, SPI Nor/SPI Nand Flash, 4NAND Flash, or PCIe slaves |
SDK • Arm CPU support Linux SMP
• DSP/MCU suooort LiteOS |
Chip Physical Specifications - Power Consumption
- 5.2W typical power consumption (4K30 + 4Tops)
- Operating Voltage
- Kernel voltage is 0.8V
- IO voltage is 1.8/3.3V
- DDR4/LPDDR4/LPDDR4x interface voltages of 1.2/1.1/0.6V respectively
- Package Format
- RoHS, FC-BGA 23mm x 23mm package
- Pin spacing: 0.65mm |
